Commit 823f7d37 authored by Silviu Baranga's avatar Silviu Baranga
Browse files

[Morello] Allow usage of ccmp for capabilities

Capability comparisons will use the VA, so we can do
this transformation by using the integer subregister.
parent a854cede
Pipeline #67648 passed with stages
in 265 minutes and 20 seconds
......@@ -2752,6 +2752,14 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
const bool FullFP16 =
static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
 
if (LHS.getValueType().isFatPointer()) {
SDValue SubReg = DAG.getTargetConstant(AArch64::sub_64, DL, MVT::i32);
LHS = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
DL, MVT::i64, LHS, SubReg), 0);
RHS = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
DL, MVT::i64, RHS, SubReg), 0);
}
if (LHS.getValueType().isFloatingPoint()) {
assert(LHS.getValueType() != MVT::f128);
if (LHS.getValueType() == MVT::f16 && !FullFP16) {
......@@ -2800,8 +2808,6 @@ static bool canEmitConjunction(const SDValue Val, bool &CanNegate,
if (Opcode == ISD::SETCC) {
if (Val->getOperand(0).getValueType() == MVT::f128)
return false;
if (Val->getOperand(0).getValueType() == MVT::iFATPTR128)
return false;
CanNegate = true;
MustBeFirst = false;
return true;
......@@ -2864,16 +2870,14 @@ static SDValue emitConjunctionRec(SelectionDAG &DAG, SDValue Val,
SDValue LHS = Val->getOperand(0);
SDValue RHS = Val->getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
bool isInteger = LHS.getValueType().isInteger();
bool isIntegerCC = LHS.getValueType().isInteger() ||
LHS.getValueType().isFatPointer();
if (Negate)
CC = getSetCCInverse(CC, LHS.getValueType());
SDLoc DL(Val);
// Determine OutCC and handle FP special case.
if (isInteger) {
if (isIntegerCC) {
OutCC = changeIntCCToAArch64CC(CC);
} else if (LHS.getValueType().isFatPointer()) {
// We have no support for conditionnal compares with capabilities.
llvm_unreachable("Not a conjunction disjunction tree");
} else {
assert(LHS.getValueType().isFloatingPoint());
AArch64CC::CondCode ExtraCC;
......
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -debugify-and-strip-all-safe -target-abi purecap -march=aarch64 -mattr=+morello,+c64 | FileCheck %s
target datalayout = "e-m:e-pf200:128:128:128:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-A200-P200-G200"
target triple = "aarch64-none-unknown-elf"
define i8 addrspace(200)* @foo(i32 addrspace(200)* readnone %x, i32 addrspace(200)* readnone %y, i32 addrspace(200)* readnone %z, i32 addrspace(200)* readnone %u) local_unnamed_addr addrspace(200) #0 {
; CHECK-LABEL: foo:
; CHECK: .Lfunc_begin0:
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: cmp x1, x2
; CHECK-NEXT: ccmp x0, x3, #0, ne
; CHECK-NEXT: csel c0, c0, c2, ne
; CHECK-NEXT: ret c30
entry:
%cmp.not = icmp ne i32 addrspace(200)* %x, %u
%cmp1 = icmp eq i32 addrspace(200)* %y, %z
%or.cond = select i1 %cmp.not, i1 true, i1 %cmp1
%cond = select i1 %or.cond, i32 addrspace(200)* %x, i32 addrspace(200)* %z
%0 = bitcast i32 addrspace(200)* %cond to i8 addrspace(200)*
ret i8 addrspace(200)* %0
}
attributes #0 = { nounwind }
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